1. Field of the Invention
The present invention relates to an integrated circuit (IC) having a voltage regulator used with a memory.
2. Description of the Related Art
Non-volatile memory is used in applications where it is desired to retain the information stored in the memory even if power is not applied. Various types of integrated circuit technologies have been devised to implement non-volatile memory, with the electrically erasable programmable read-only memory (EEPROM) being of significant commercial interest. EEPROMs rely on charge injection to a charge storage region, typically a floating (e.g., insulated) gate for storing the charge that determines whether a logic "1" or "0" is stored in the case of a binary memory. However, more than two levels of stored charge are possible for multi-level memory cells that store more than two logic levels. A particular form of EEPROM, referred to as "flash" memory, allows for erasing an entire memory array or sub-array. This is a much faster operation than if each memory cell in the array were erased independently.
To program the EEPROM cell, a high voltage of a given polarity with respect to the tub is applied to the drain junction, in order to inject charge to the floating gate. Regulating the programming voltage by a zener diode formed concurrently in a flash memory process has been used for conventional channel hot electron injection, such as described in U.S. Pat. No. 5,103,425. To erase the cell, a high voltage of the opposite polarity is applied to the gate in order to remove the stored charge. The write/erase programming operation in an EEPROM cell is typically much slower than a read operation that retrieves information from the cell, and so efforts have been made to maximize the programming speed.
One form of floating-gate memory suitable for implementing a flash memory array utilizes secondary electron injection to assist in programming a memory cell. This technique allows for the use of a lower voltage for programming the cell as described in U.S. Pat. No. 5,659,504 "Method and Apparatus for Hot Carrier Injection", co-assigned herewith, and which is incorporated herein by reference. In order to generate sufficient number of secondary electrons, the drain-to-tub junction of an EEPROM cell is reverse biased into the sub-breakdown regime, which is about 0.5V-1.0V below the real breakdown voltage. The closer the junction is biased to breakdown, the faster the programming, but the less the margin of program disturb. To program a positive logic "1" into the cell in one present-day implementation, approximately -3 volts is applied to the tub in which the memory cells are located, and about+3 volts is applied to the bit line, which is connected to the drains of the memory cells. In order to erase the cell (i.e., write a positive logic "0"), the memory tub is typically biased to about +10 volts and the gate to about -8 volts, both with respect to the wafer substrate at 0 volts. This removes the charge on the floating gate, being electrons in the case of an n-channel memory device. In this regime the programming speed and disturb margin of the flash memory device is very sensitive to supply voltage fluctuations and manufacturing process variations which could change the abruptness of the drain junction.
When reading the cell, about +1 volts are applied to the bit line, and 0 volts applied to the memory cell tub with respect to the wafer substrate. However, the drain-to-tub bias voltage is not applied during reading, since secondary electrons do not need to be generated.